digital adder

基本解释

Addend and the summand input, and digital and carry the output device is a half adder.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器为例介绍其在数字系统设计和数字电路实验及教学中的应用。